ISD-VM1110A (276-1324) Operation Faxback Doc. # Operation The ISD-VM1110A Chip-On-Board module is controlled by a single signal, REC, and either of two push-button control playback signals, PLAYE* (edge-activated playback), and PLAYL* (level-activated playback). Module operation is explained on page 4. Speech Quality patented ChipCorder technology provides natural sound quality record and playback. The input voice signals are stored directly in nonvolatile EEPROM cells and are reproduced without the synthetic effect often heard with digital solid-state speech solutions. A complete sample is stored in a single cell, minimizing the memory necessary to store a recording of a given duration. Automatic Power-Down Mode: At the end of a Playback or Record cycle, the ISD-VM1110A module automatically returns to a low-power standby mode, consuming typically 0.5 mA. During a Playback cycle, the device powers down automatically at the end of the message. During a Record cycle, the device powers down after REC is released and immediately pulled HIGH. Although the module powers down automatically to conserve power consumption, the typical drain on the battery when driving 16-ohm speakers to full volume averages 30 to 40 mA. This must be taken into consideration when selecting batteries with their inherent internal resistance. Mounting Options The ISD-VM1110A module is designed with several mounting options. The edge connector has been designed to use a standard 15 dual position .050 series connector, (AMP 650712 or equivalent). Additionally, a series of through holes are also placed in the board to accept a standard 100-mil grid headers (Molex 8624 or equivalent). These holes may also be used for hard-wire connection to the board. Addressing (Optional) In addition to providing simple message playback, the ISD-VM1110A provides a full addressing capability. 20 The ISD-VM1110A module has 80 distinct addressable segments providing 125 ms resolution per segment. See the ISD Application Notes and Design Manual booklet for ISD1110 address tables. PIN DESCRIPTIONS; Note: The REC*, PLAYL**, and PLAYE* signals are all debounced for 50 ms on the rising edge to prevent a false retriggering from a push-button switch. REC*, PLAYL**, PLAYE**, A6 and A7 have internal pullups to VCC. Holding one of these pins LOW will increase standby current consumption. A0, A1, A2, A3, A4, A5 and XCLK have internal pulldown to VSS. Holding one of these pins HIGH will increase standby current consumption. Pin 12: Record (REC*) The REC input is an active-LOW Record signal. The device records whenever REC* is LOW. This signal must remain LOW for the duration of the Recording. REC* takes precedence over either Playback (PLAYE* or PLAYL**) signal. If REC* is pulled LOW during a Playback cycle, the Playback immediately ceases and Recording begins. A Record cycle is completed when REC* is pulled HIGH or the memory space is filled. An end-of-message marker is internally recorded, enabling a subsequent Playback cycle to terminate appropriately. The device automatically powers down to standby mode when REC* goes HIGH. This pin has an internal pull-up device. Pin 10: Playback, Edge-Activated (PLAYE**) When a LOW-going transition is detected on this input signal, a Playback cycle begins. Playback continues until an end-of-message marker is encountered or the end of the memory space is reached. Upon completion of the Playback cycle, the device automatically powers down into standby mode. Taking PLAYE* HIGH during a Playback cycle will not terminate the current cycle. This pin has an internal pull-up device. Pin 9: Playback, Level-Activated (PLAYL**) When this input signal transitions from HIGH to LOW, a Playback cycle is initiated. Playback continues until PLAYL* is pulled HIGH, an end-of-message marker is detected, or the end of the memory space is reached. The device automatically powers down to standby mode upon completion of the Playback cycle. This pin has an internal pull-up device. Note: In Playback, if either PLAYE* or PLAYL* is held LOW at the end of the message, the module will still enter standby and the internal oscillator and timing generator will stop. However, the rising edge of PLAYE* and PLAYL* will no longer be debounced, and any subsequent falling edge present on the input pins will initiate another playback. Pin 11: Record LED Output (RECLED*) The output RECLED* is LOW during a Record cycle. It can be used to drive an LED to provide feedback that a Record cycle is in progress. In addition, RECLED* pulses LOW momentarily when an end-of-message marker is encountered in a Playback cycle. Pin 7: Microphone Input (MIC +) An electret microphone (the positive terminal) is connected to this pin with a maximum input signal of 20 mV peak-to-peak. The microphone input (MIC +) provides an Automatic Gain Control (AGC) to dynamically adjust the preamplifier gain, and therefore extend the range of input signals which can be applied to the microphone input without causing distortion. The AGC considerably extends the dynamic range of recordable sound from whispers to loud voices. Pin 6: Microphone Reference (MIC-) This Pin is the negative connection for the two-terminal electret microphone. Pin 8: Analog Input (ANA IN) The ANA IN pin may be used to input alternative sources of analog signals (instead of the microphone signal) at a maximum of 50 mV peak-to-peak. [If this pin is not used, it must NOT be connected to any signal or voltage. It must float.] Pins 4, 5: Speaker Outputs (SPKR+, SPKR -) The SPKR+ and SPKR - pins provide direct drive for loudspeakers with impedances as low as 16 ohms. A single output may be used, but, for direct-drive loudspeakers, the two opposite-polarity outputs provide an improvement in output power of up to four times over a single-ended connection. Furthermore, when SPKR+ and SPKR - are used, a speaker coupling capacitor is not required. A single-ended connection will require an AC-coupling capacitor between the SPKR pin and the speaker. The speaker outputs are in a high-impedance state during a Record cycle, and held at VSS/GND (BATT-) during Power Down. Pin 19: Optional External Clock This pin is held LOW by an internal pulldown; however, if greater timing precision is desired, the chip can be externally clocked through this pin. The internal clock has a + 2.5 % tolerance over temperature and voltage range. Pin 13, 18: Vcc (BATT+) Analog and digital circuits internal to the ISD1110 chip use separate power buses on the module, to minimize noise on the chip. These power buses are on separate traces and are decoupled on the module. The power buses are tied together at the BATT+ pin. Pin 3, 28: VSS/GND (BATT -) Similar to VCC, the analog and digital circuits internal to the chip use separate ground buses on the module, to minimize noise. These ground buses are tied together at the BATT- pin. Pins 20-27: Address Inputs (A0-A7) The Address Inputs have two functions, depending upon the level of the two Most Significant Bits (MSB) of the address (A6 and A7). If either of the two MSBs is LOW, the inputs are ALL interpreted as address bits and are used as the start address for the current Record or Playback cycle. The address pins are inputs only and do not output internal address information as the operation progresses. Address inputs are latched by the falling edge of PLAYE*, PLAYL* or REC*. A6 and A7 have internal pull-up devices. A0, A1, A2, A3, A4 and A5 have internal pulldown devices. Address Termination The ISD-VM1110A was designed with internal terminating resistors for all the addresses and control lines. This allows the signals to be left floating if not used. A0, A1, A2, A3, A4, A5 and XCLK are pulled LOW and A6, A7, PLAYL*, PLAYE* and REC* are pulled HIGH. Each of these internal pull-up or pulldown resistors have a value of 50K to 100K ohms. OPERATIONAL MODE The ISD-VM1110A module is designed with a built-in operational mode that enables the continuous repetition of a single message. This operational mode uses the address pins on the ISD-VM1110A module, but is mapped outside the valid address range. When the two Most Significant Bits (MSBs) are HIGH, the remaining address signals are interpreted as mode bits and NOT as address bits. Therefore, the operational mode and direct addressing are not compatible and cannot be used simultaneously. Looping Capability The ISD-VM1110A Module has a built-in looping function enabling it to continuously repeat a single message. This is accomplished by taking A3 HIGH to continuously loop from the end of the message to the beginning of the message space. Looping is initiated by a negative transition on PLAYE* pin with A7, A6 and A3 held HIGH. Then PLAYE* is brought back HIGH. Looping will continue indefinitely with all three control pins (PLAYL*, PLAYE*, REC*) remaining HIGH. To stop the looping, PLAYL* pin is momentarily taken LOW, then back HIGH. As long as A7, A6 and A3 remain HIGH, a new playback loop will begin with the next negative transition on the PLAYE* pin. Another way to control looping is to use PLAYL* pin alone. Taking this pin LOW begins the looping and it continues until the pin is taken HIGH again. This is a continuous control rather than the pulsed control of the previous paragraph. MODULE OPERATION EXAMPLE The following example operating sequence demonstrates the functionality of the ISD-VM1110A module. 1. Record a message filling the memory. Pulling the REC* signal LOW initiates a Record cycle from the beginning of the message space. If REC* is held LOW, the Recording continues until the message space has been filled. Once the message space is filled, Recording ceases. The device will automatically power down after REC is released HIGH (disconnected). 2. Edge-activated Playback. Pulling the PLAYE* signal LOW initiates a Playback cycle from the beginning of the message memory or at a selected location. The rising edge of PLAYE* has no effect on operation. If a Recording has filled the message space, the entire message is played. When the device reaches the EOM marker, it automatically powers down. A subsequent falling edge on PLAYE* initiates a new Play cycle from the beginning of the message memory. 3. Level-activated Playback. Pulling the PLAYL* signal LOW initiates a Playback cycle from the beginning of the message memory or a selected location. If recording has filled the message space, the entire message is played. When the device reaches the EOM marker, it automatically powers down. A subsequent falling edge on PLAYL* initiates a new Play cycle from the beginning of the message memory. 4. Level-activated Playback (truncated). If PLAYL* is pulled HIGH any time during the Playback cycle, the device stops playing and enters the power-down mode (i.e. useful for push-button interface). 5. Record (interrupting Playback) The REC* signal takes precedence over other operations. Any LOW-going transition on REC* initiates a new record operation from the beginning of the memory, or at a selected location, regardless of any current operation in progress. 6. Record a message, partially filling the memory. A record operation does not necessarily fill the entire memory. Releasing the REC signal HIGH before filling the message space causes the recording to stop and an end-of-message marker to be placed. The device powers down automatically. 7. Play back a message which partially fills the memory. Pulling the PLAYE* or PLAYL* signal LOW initiates a Playback cycle. This cycle is then completed when the end-of-message marker is encountered. Playback ceases and the device powers down. 8. RECLED* operation. The RECLED* output pin provides an active-LOW signal which can be used to drive an LED as a "record-in-progress" indicator. It returns to a HIGH state when the pin is released HIGH, or when the recording is completed due to the memory being filled. The module has a 1 KW resistor in series with this pin for LED current limiting. This pin also pulses LOW to indicate an EOM at the end of a message being played. (JLC-04/13/95)