TLC555 Timer
(276-1718)                 Features                   Faxback Doc. # 31976

The TLC555 is a monolithic timing circuit fabricated using the LinCMOS*
process.  Due to its high-impedance inputs (typically 10^12 Ohm), it
is capable of producing accurate time delays and oscillations while using
less expensive, smaller timing capacitors than the NE555.  Like the NE555,
the TLC555 achieves both monostable (using one resistor and one capacitor)
and astable (using two resistors and one capacitor) operation.  In
addition, 50% duty cycle astable operation is possible using only a single
resistor and one capacitor.  Operates at frequencies up to 2 MHz and is
fully compatible with CMOS, TTL, and MOS logic.  It also provides very
low power consumption (typically 1 mW at V^DD=5V) over a wide range of
supply voltages ranging from 2 volts to 18 volts.

Like the NE555, the threshold and trigger levels are normally two-thirds
and one-third respectively of V^DD.  These levels can be altered by use of
the control voltage terminal.  When the trigger input falls below trigger
level, the flip-flop is set and the output goes high.  If the trigger
input is above the trigger level and the threshold input is above the
threshold level, the flip-flop is reset and the output is low.  The reset
input can override all other inputs and can be used to initiate a new
timing cycle.  When the reset input goes low, the flip-flop is reset and
the output goes low.  Whenever the output is low, a low impedance path is
provided between the discharge terminal and ground.

While the complementary CMOS output is capable of sinking over 100mA and
sourcing over 10 mA, the TLC555 exhibits greatly reduced supply current
spikes during output transitions.  This minimizes the need for the large
decoupling capacitors required by the NE555.

*  LinCMOS is a trademark for a silicon-gate IC process by Texas
   Instruments.


(LB-03/23/95)